It is widely recognized that GaAs MOSFETs potentially could have desirable properties, e.g., speed in excess of that of conventional (Si-based) MOSFETs, low power consumption and circuit simplicity (if complementary MOSFETs were available). However, until recently attempts to make such devices did not result in devices having commercially acceptable properties, typically due to low quality of the gate oxide. In particular, acceptable enhancement mode devices were not available.
Recently significant progress was made towards solution of the gate oxide problem. See, for instance, U.S. patent application Ser. No. 08/408,678, filed Mar. 22, 1995 by M. Hong et al. See also U.S. Pat. Nos. 5,550,089 and 5,451,548. Indeed, U.S. patent application Ser. No. 08/741,010, filed Oct. 31, 1996 by Y. K. Chen et al., discloses a planar, enhancement mode GaAs MOSFET with inversion channel, and a method of making the MOSFET. Such a device is particularly desirable for circuit applications. It is "normally off", i.e., non-conducting with zero applied gate voltage. All of the above cited patents and patent application are incorporated herein by reference.
Despite the recent advances, it would still be desirable to provide improved GaAs-based MOSFETs, including planar, enhancement mode GaAs-based MOSFETs, and/or an improved method of making such MOSFETs. This application discloses such a device and such a method of making the device.